The Transistor — Question 4

Question 4

The collector load line limits an amplifier voltage swing

An emitter-grounded NPN stage has $V_{CC}=12.0\,\mathrm V$ and $R_C=2.00\,\mathrm{k\Omega}$. Use cutoff $I_C=0$ and saturation limit $V_{CE,\mathrm{sat}}=.200\,\mathrm V$. Neglect Early effect.

1. Find the two endpoints of the dc load line.

2. Choose the quiescent collector voltage for the largest symmetric output-voltage swing and find its collector current and maximum undistorted sinusoidal peak amplitude in this idealized model.

Question 4 - Solution

The collector load line limits an amplifier voltage swing

(a) Method and calculation

$$V_{CE}=V_{CC}-I_CR_C\Rightarrow\boxed{(V_{CE},I_C)_{\mathrm{cutoff}}=(12.0\,\mathrm V,0)}.$$$$\boxed{I_{C,\mathrm{sat}}=(12.0-.200)/2000=5.90\,\mathrm{mA}}.$$

(b) Interpretation and further calculation

$$\boxed{V_{CE,Q}=(12.0+.200)/2=6.10\,\mathrm V,\quad I_{C,Q}=2.95\,\mathrm{mA}}.$$$$\boxed{v_{o,\mathrm{pk}}=\min(12.0-6.10,6.10-.200)=5.90\,\mathrm V}.$$

Physical check

The symmetric midpoint includes the nonzero saturation voltage. Real low-distortion swing is smaller because transistor behavior changes before an ideal hard clipping boundary.